This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2002-206177, filed Jul. 15, 2002; and No. 2003-193728, filed Jul. 8, 2003, the entire contents of both of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory. More specifically, the invention relates to a multilevel flash memory wherein a multi-level of three or more levels is stored in a single cell.
2. Description of the Related Art
A binary flash memory for storing two data items of different levels (referred to as binary data hereinafter) widely spreads as a nonvolatile semiconductor memory.
FIG. 16 shows the arrangement of the main part of a binary flash memory (e.g., a NOR type). Referring to FIG. 16, a cell array 101 includes a plurality of memory cells (main cells) MC arranged in matrix. The control gates of memory cells MC arranged in one row are connected to a common one of a plurality of word lines WL0 to WLn. The drain regions of memory cells MC arranged in one column are connected to a common one of a plurality of bit lines BL0 to BLk. Generally, the cell array 101 is divided into a plurality of blocks. The source regions of memory cells MC in one block are connected to a common one of a plurality of source lines (not shown). The bit lines BL0 to BLk are connected to a sense amplifier 102 through their corresponding one of a plurality of select transistors ST0 to STk. A plurality of column lines COL0 to COLm are connected to the gates of the select transistors ST0 to STk, respectively.
A reference circuit 103 includes one reference cell RC and a plurality of dummy cells DC. The drain regions of the reference cell RC and dummy cells DC are connected to each other. The control gate of the reference cell RC is connected to a reference word line RWL. The drain region of the reference cell RC is connected to the sense amplifier 102 via an n-type MOS transistor 103a. A reference column line RCOL is connected to the gate of the transistor 103a. 
The sense amplifier 102 includes n-type MOS transistors 102a and 102b, p-type MOS transistors 102c and 102d and a differential amplifier 102e. The source region of the n-type MOS transistor 102a is connected to the drain regions of the select transistors ST0 to STk in the cell array 101. The drain region of the n-type MOS transistor 102a is connected to the gate and the drain region of the p-type MOS transistor 102c and the inverted input terminal of the differential amplifier 102e. On the other hand, the source region of the n-type MOS transistor 102b is connected to the drain region of the n-type MOS transistor 103a in the reference circuit 103. The drain region of the n-type MOS transistor 102b is connected to the gate and the drain region of the p-type MOS transistor 102d and the noninverted input terminal of the differential amplifier 102e. The differential amplifier 102e outputs sensed cell data (Dout) from its output terminal.
A BIAS power supply voltage is applied to the gate of each of the n-type MOS transistors 102a and 102b. A power supply voltage Vcc is applied to the source region of each of the p-type MOS transistors 102c and 102d. 
FIG. 17 shows the characteristics of the binary flash memory with the above arrangement. More specifically, FIG. 12 shows a relationship (Vg-Icell (Id) characteristics) between a gate voltage Vg applied to the control gate and a cell current Icell (drain current Id) per load current in both the memory cell MC and the reference cell RC. In data read and program verify modes, a read voltage Vr is applied to the control gate of the reference cell RC. Thus, the sense amplifier 102 always determines the cell current Icell (xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d) by the reference current Iref.
In the Vg-Id characteristics of the memory cell MC, the state of a relatively large number of electrons stored in a floating gate (or a high threshold voltage Vth of the memory cell MC) is considered to be data xe2x80x9c0xe2x80x9d. The memory cell MC that stores the data xe2x80x9c0xe2x80x9d is referred to as a xe2x80x9c0xe2x80x9d cell. Conversely, the state of a relatively small number of electrons (or a low threshold voltage Vth of the memory cell MC) is considered to be data xe2x80x9c1xe2x80x9d. The memory cell MC that stores the data xe2x80x9c1xe2x80x9d is referred to as a xe2x80x9c1xe2x80x9d cell.
The cell current of the reference cell RC (reference current Iref) is set to approximately half the cell current Icell of the memory cell MC. In other words, when the gate voltage Vg is equal to the read voltage Vr, a difference between the cell current Icell of the memory cell MC and the cell current Iref of the reference cell RC in the xe2x80x9c0xe2x80x9d cell and that in the xe2x80x9c1xe2x80x9d cell are almost equal to each other.
FIG. 18 shows a correlation between the gate voltage (Vg-hontai) of the memory cell MC and the gate voltage (Vg-ref) of the reference cell RC in each of operating modes. For example, in program verify (PV) mode for defining a data program state xe2x80x9c0xe2x80x9d, a program verify voltage Vpv (=6.5V) is applied to the control gate of the memory cell MC. A difference between the program verify voltage Vpv and the read voltage Vr (=5.5V) that is applied to the control gate of the reference cell RC is reflected in the threshold voltage Vth of the memory cell MC. Thus, the xe2x80x9c0xe2x80x9d cell is usually cut off when the gate voltage Vg is equal to the read voltage Vr. Similarly, for example, in erase verify mode (EV) mode for defining a data erase state xe2x80x9c1xe2x80x9d, an erase verify voltage Vev (=4V) is applied to the control gate of the memory cell MC. If the erase verify voltage Vev is set at roughly the same as the reference voltage Vtref, the current flowing when the gate voltage Vg of the xe2x80x9c1xe2x80x9d cell is equal to the read voltage Vr, i.e., the cell current Icell becomes almost equal to 2Iref.
In other words, the sense amplifier 102 senses a current difference (+Iref/xe2x88x92Iref) between the cell current Icell of the memory cell MC and the cell current Iref of the reference cell RC, which is caused when the gate voltage Vg is equal to the read voltage Vr and converts it into a digital signal of xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d. Accordingly, cell data is read out.
FIG. 19 shows the distribution of threshold voltages Vth with respect to the gate voltage Vg in the memory cell (binary cell) MC capable of storing binary data xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d. For example, in over-erase verify (OEV) mode for compensating for the lower limit of the cell distribution corresponding to the data erase state xe2x80x9c1xe2x80x9d, an over-erase verify voltage Voev (=2V), which is lower than the erase verify voltage Vev, is applied to the control gate of the memory cell MC. A cell that becomes xe2x80x9c1xe2x80x9d when the over-erase verify voltage Voev is applied is detected. Data is written such that the threshold voltage Vth of a bit corresponding to the cell becomes xe2x80x9c0xe2x80x9d when the over-erase verify voltage Voev is applied. Thus, the cell distribution corresponding to the erase state xe2x80x9c1xe2x80x9d falls within a given range.
The cell area per bit is a cost index of a flash memory. There is a multilevel flash memory that can be reduced in cost by storing data of a plurality of bits in one cell as well as by decreasing the cell area. A four-level flash memory for storing four levels or four data items of different levels (four-level data) has been already reported in, for example, M. bauer et al., xe2x80x9cA Multilevel-Cell 32Mb Flash Memoryxe2x80x9d, ISSCC Digest of Technical Papers, pp. 132-133, 1995.
The cell distribution of the four-level flash memory is discrete with respect to the gate voltage. More specifically, in verify mode, a margin for reading is secured by varying the gate voltage of a memory cell as in the binary flash memory. On the other hand, cell data is read out at a constant gate voltage.
Assuming that the memory cells vary in transconductance or the ratio of a change in cell current to that in gate voltage varies, a margin (read margin) for the reference current of read current will be lowered. The low read margin influences the read access time and causes a failure in reading.
As described above, the prior art multilevel flash memory secures a verify margin at the gate voltage. For this reason, there occurs a problem that the variations in the ratio of a change in cell current to that in gate voltage lowers the read margin.
According to a first aspect of the present invention, there is provided a nonvolatile semiconductor memory comprising: a plurality of nonvolatile memory cells each having a gate, a drain and a source to hold data corresponding to a threshold voltage level; a plurality of word lines connected to gates of the nonvolatile memory cells, respectively; a plurality of bit lines connected to drains of the nonvolatile memory cells, respectively; a plurality of source lines connected to sources of the nonvolatile memory cells, respectively; a reference current generation circuit which generates a reference current, the reference current generation circuit including at least one reference cell and an amplification circuit which amplifies a current flowing through the reference cell, and a ratio of an amplification factor of current in a program verify mode to an amplification factor of current in a data read mode is larger than 1; and a sense amplifier which compares the reference current with a current flowing through selected ones of the nonvolatile memory cells and reads data held in the selected ones of the nonvolatile memory cells.
According to a second aspect of the present invention, there is provided a nonvolatile semiconductor memory comprising: a plurality of nonvolatile memory cells each having a gate, a drain and a source to hold a multilevel of three or more levels corresponding to a threshold voltage level; a plurality of word lines connected to gates of the nonvolatile memory cells, respectively; a plurality of bit lines connected to drains of the nonvolatile memory cells, respectively; a plurality of source lines connected to sources of the nonvolatile memory cells, respectively; a reference current generation circuit which generates at least first and second reference currents, the reference current generation circuit including at least a first reference cell, a second reference cell having a threshold voltage that is higher than that of the first reference cell, a first amplification circuit which amplifies a current flowing through the first reference cell, and a second amplification circuit which amplifies a current flowing through the second reference cell, a first current amplification ratio of an amplification factor of current in program verify mode to an amplification factor of current in a data read mode in the first amplification circuit being larger than 1, a second current amplification ratio of an amplification factor of current in a program verify mode to an amplification factor of current in a data read mode in the second amplification circuit being larger than 1, and the first current amplification ratio being smaller than the second current amplification ratio; a first sense amplifier which compares the first reference current with a current flowing through a selected one of the nonvolatile memory cells and reads a signal corresponding to a multilevel held in the selected one of the nonvolatile memory cells; and a second sense amplifier which compares the second reference current with a current flowing through a selected one of the nonvolatile memory cells and reads a signal corresponding to a multilevel held in the selected one of the nonvolatile memory cells.
According to a third aspect of the present invention, there is provided a nonvolatile semiconductor memory comprising: a plurality of nonvolatile memory cells each having a gate, a drain and a source to hold a multilevel of three or more levels corresponding to a threshold voltage level; a plurality of word lines connected to gates of the nonvolatile memory cells, respectively; a plurality of bit lines connected to drains of the nonvolatile memory cells, respectively; a plurality of source lines connected to sources of the nonvolatile memory cells, respectively; a reference current generation circuit which selectively generates at least first and second reference currents, the reference current generation circuit including at least a first reference cell, a second reference cell having a threshold voltage that is higher than that of the first reference cell, a first amplification circuit which amplifies a current flowing through the first reference cell, and a second amplification circuit which amplifies a current flowing through the second reference cell, a first current amplification ratio of an amplification factor of current in program verify mode to an amplification factor of current in a data read mode in the first amplification circuit is larger than 1, a second current amplification ratio of an amplification factor of current in a program verify mode to an amplification factor of current in a data read mode in the second amplification circuit is larger than 1, and the first current amplification ratio is smaller than the second current amplification ratio; and a sense amplifier which compares an output current of the reference current generation circuit and a cell current flowing through a selected one of the nonvolatile memory cells and amplifies and outputs the cell current.
According to a fourth aspect of the present invention, there is provided a nonvolatile semiconductor memory comprising: a plurality of nonvolatile memory cells each having a gate, a drain and a source to hold a multilevel of three or more levels corresponding to a threshold voltage level; a plurality of word lines connected to gates of the nonvolatile memory cells, respectively; a plurality of bit lines connected to drains of the nonvolatile memory cells, respectively; a plurality of source lines connected to sources of the nonvolatile memory cells, respectively; a reference current generation circuit which selectively generates at least first and second reference currents, the reference current generation circuit including at least a first reference cell, a second reference cell having a threshold voltage that is higher than that of the first reference cell, a first amplification circuit which amplifies a current flowing through the first reference cell, and a second amplification circuit which amplifies a current flowing through the second reference cell, a first current amplification ratio of an amplification factor of current in program verify mode to an amplification factor of current in a data read mode in the first amplification circuit being larger than 1, a second current amplification ratio of an amplification factor of current in a program verify mode to an amplification factor of current in a data read mode in the second amplification circuit being larger than 1, and the first current amplification ratio is smaller than the second current amplification ratio, the reference current generation circuit further including a third reference cell having a threshold voltage which is higher than that of the second reference cell in order to generate a third reference current, and a third amplification circuit which amplifies a current flowing through the third reference cell; and a sense amplifier which compares an output current of the reference current generation circuit and a cell current flowing through a selected one of the nonvolatile memory cells and amplifies and outputs the cell current, wherein the reference current generation circuit selectively outputs the second and third reference currents in accordance with logic of an output of the sense amplifier when the output current of the reference current generation circuit is the first reference current.
According to a fifth aspect of the present invention, there is provided a nonvolatile semiconductor memory comprising: a plurality of memory cells each having 2N (N is two or more) levels; a plurality of word lines connected to gates of the memory cells, respectively; a plurality of bit lines connected to drains of the memory cells, respectively; a plurality of source lines connected to sources of the memory cells, respectively; a reference current generation circuit which selectively outputs one of (Nxe2x88x921) reference currents, the reference current generation circuit including (Nxe2x88x921) reference cells and (Nxe2x88x921) amplification circuits which amplify a current flowing through the (Nxe2x88x921) reference cells, a threshold voltage of a first reference cell of the (Nxe2x88x921) reference cells being higher than that of a (Ixe2x88x921)-th reference cell (1xe2x89xa6Ixe2x89xa6N), a ratio of an I-th amplification factor of current in program verify mode to an amplification factor of current in a data read mode in an I-th amplification circuit of the (Nxe2x88x921) amplification circuits being larger than 1, and a (Ixe2x88x921)-th amplification factor being smaller than the I-th amplification factor; and a sense amplifier which compares an output current of the reference current generation circuit and a cell current flowing through a selected one of the memory cells and amplifies and outputs the cell current, wherein the reference current generation circuit selectively outputs the second and third reference currents in accordance with logic of an output of the sense amplifier when the output current of the reference current generation circuit is the first reference current.
According to a sixth aspect of the present invention, there is provided a nonvolatile semiconductor memory comprising: a plurality of memory cells each having 2N (N is two or more) levels; a plurality of word lines connected to gates of the memory cells, respectively; a plurality of bit lines connected to drains of the memory cells, respectively; a plurality of source lines connected to sources of the memory cells, respectively; a reference current generation circuit which selectively outputs one of (Nxe2x88x921) reference currents, the reference current generation circuit including (Nxe2x88x921) reference cells and (Nxe2x88x921) amplification circuits which amplify a current flowing through the (Nxe2x88x921) reference cells, a threshold voltage of a first reference cell of the (Nxe2x88x921) reference cells being higher than that of a (Ixe2x88x921)-th reference cell (1xe2x89xa6Ixe2x89xa6N), a ratio of an I-th amplification factor of current in program verify mode to an amplification factor of current in a data read mode in an I-th amplification circuit of the (Nxe2x88x921) amplification circuits being larger than 1, and a (Ixe2x88x921)-th amplification factor being smaller than the I-th amplification factor; and a sense amplifier which compares an output current of the reference current generation circuit and a cell current flowing through a selected one of the memory cells and amplifies and outputs the cell current, wherein the reference current generation circuit selectively outputs the second and third reference currents in accordance with logic of an output of the sense amplifier when the output current of the reference current generation circuit is the first reference current.